Latency Numbers Every Programmer Should Know (Interactive)
Visualize the physical orders of magnitude between CPU registers, RAM, SSDs, and cross-continent network packets. Interactive benchmark scale visualizer comparing L1 cache references (0.5 ns), main memory RAM access (100 ns), NVMe SSD reads (10 µs), and cross-continental network round-trips (150 ms).
Latency Numbers Visualizer ⏱️
Scale nanosecond hardware delays into intuitive human time (1 CPU cycle = 1 second).
1 CPU Clock Cycle (3.3 GHz)
The fundamental heartbeat of modern silicon processors executing a single instruction.
1 Second
If fetching from CPU register takes 1 second, this operation feels like waiting 1 Second to the processor!
Architectural Insight:
Reading from RAM is like a 5-minute coffee break; reading from spinning disk is waiting 10 months; cross-ocean network calls are a 16-year career!
How It Works Under the Hood
Hardware physics dictates the boundary conditions of all distributed system architectures. An engineer who does not possess an instinctive feel for hardware latency orders of magnitude cannot accurately calculate back-of-the-envelope capacity numbers. An L1 CPU cache reference takes approximately 0.5 nanoseconds. Reading 1 MB sequentially from RAM takes ~3,000 nanoseconds (3 microseconds). Reading 1 MB sequentially from a fast NVMe SSD takes ~200,000 nanoseconds (200 microseconds). Sending a packet round-trip from California to the Netherlands takes 150,000,000 nanoseconds (150 milliseconds). If an L1 cache access were equivalent to 1 human second, a round-trip across the Atlantic Ocean would be equivalent to almost 10 years.
Core Architectural Principles
- Orders of magnitude: Nanoseconds (10^-9s) for CPU/RAM, Microseconds (10^-6s) for SSDs/Local LAN, Milliseconds (10^-3s) for WAN/Internet.
- Sequential vs Random I/O: Sequential disk/memory throughput is 10x to 100x faster than random seek operations.
- Speed of light in fiber optic glass: ~200,000 km/s (roughly 5 microseconds per kilometer of cable distance).
Use these numbers during the first 5 minutes of your interview when calculating back-of-the-envelope capacity. Estimating memory cache requirements using 80/20 rules and recognizing that disk seeks are 100,000x slower than memory lookups demonstrates staff-level engineering instinct.
In-memory architectures provide microsecond response times but carry high RAM hardware costs vs disk-backed NVMe storage with higher latency.